RE: [sv-ec] Compilation unit query

Dave,
Thanks for your reply, but the logic is not clear to me.
If the semantic of $unit::b is same as hierarchical ref. Then what was the
reason of
Creating a new syntax for this.
Also syntax wise it is similar to access a variable from a package than a
hier ref.

Another point is definition of $unit ( compilation unit ) is tool specific.
So defining semantics of $unit::b like hier ref may cause different output
in different
Simulator.
So I think it is better to define $unit::b as an object of nearest already
visible "b".  

Thanks
Kausik


-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Rich,
Dave
Sent: Monday, March 14, 2005 7:11 PM
To: kausikd@cal.interrasystems.com; Sv-Ec
Subject: RE: [sv-ec] Compilation unit query

I think your example should be legal because it is no different than a
hierarchical reference in Verilog:

module top;

reg a;
initial a = top.b; // just b would be illegal

reg b;
initial b = a;

endmodule


Note that you couldn't do this with a type identifier because you can only
use a simple identifier to declare an object $unit::typename I; //is not
legal

Dave


________________________________________
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Kausik
Datta
Sent: Sunday, March 13, 2005 11:44 PM
To: 'Sv-Ec'
Subject: [sv-ec] Compilation unit query

Hi,
I have a query related to the compilation unit. 
Is the following testcase valid? 
module top;
 wire w1;
 assign w1 = $unit::w; // compilation unit scope endmodule reg w; Here "w"
is delared after it is used in the text. 
Thanks
Kausik 

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