RE: [sv-ec] Compilation unit query

I think your example should be legal because it is no different than a hierarchical reference in Verilog:

module top;

reg a;
initial a = top.b; // just b would be illegal

reg b;
initial b = a;

endmodule


Note that you couldn't do this with a type identifier because you can only use a simple identifier to declare an object
$unit::typename I; //is not legal

Dave


________________________________________
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Kausik Datta
Sent: Sunday, March 13, 2005 11:44 PM
To: 'Sv-Ec'
Subject: [sv-ec] Compilation unit query

Hi, 
I have a query related to the compilation unit. 
Is the following testcase valid? 
module top; 
 wire w1; 
 assign w1 = $unit::w; // compilation unit scope 
endmodule 
reg w; 
Here "w" is delared after it is used in the text. 
Thanks 
Kausik 

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