[sv-ec] Query on interface

I have a query related to declaration of modport
inside an interface.

Is it mandatory to include all signals of the interface
in the modport declaration? In other words, can we form
a modport declaration with a subset of signals declared
in the interface?

For example,

interface i1;
  wire a, b, c, d;
  modport master(output a, input b);  <--- Is this valid?
endinterface

Thx,
Swapnajit.