[sv-ec] final blocks in testbench

Hi folks,

The Accellera System Verilog 3.1a standard appears to only allow final 
blocks in modules and interfaces - not in programs. To me, this appears 
to make it difficult to specify any end-of-simulation behavior for the 
testbench to execute in the reactive region.  Have I misinterpreted the 
standard? Is this changed in the current p1800 draft? Is there a better 
way to specify end-of-sim behavior for the testbench?

Thanks,
Mike