Michael, I believe omitting final blocks from program is a BNF mistake. Arturo ----- Original Message ----- From: "Michael Burns" <michael.burns@freescale.com> To: <sv-ec@eda.org> Sent: Wednesday, February 23, 2005 11:13 AM Subject: [sv-ec] final blocks in testbench Hi folks, The Accellera System Verilog 3.1a standard appears to only allow final blocks in modules and interfaces - not in programs. To me, this appears to make it difficult to specify any end-of-simulation behavior for the testbench to execute in the reactive region. Have I misinterpreted the standard? Is this changed in the current p1800 draft? Is there a better way to specify end-of-sim behavior for the testbench? Thanks, MikeReceived on Wed Feb 23 11:24:45 2005
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