Re: [sv-ec] final blocks in testbench

>The Accellera System Verilog 3.1a standard appears to only allow final 
>blocks in modules and interfaces - not in programs. To me, this appears 
>to make it difficult to specify any end-of-simulation behavior for the 
>testbench to execute in the reactive region.  Have I misinterpreted the 
>standard?

This may have been the result of programs and final blocks being added
independently, each not taking the other feature into account.  However,
I can see potential problems with final blocks in programs.

From what you have said, it seems that you would expect a final block
in a program to execute in the reactive region.  But that would violate
the specified behavior of final blocks from section 8.7.  Once the final
blocks start executing, nothing else is supposed to execute before the
simulator exits.  But to execute program final blocks in the reactive
region would require continuing simulation after the module final blocks
finished, to reach the reactive region so that the program final blocks
can execute.  If no simulation processes are allowed to run between
these two sets of final blocks, then the concept of program final blocks
executing in the reactive region is meaningless.  If simulation processes
are allowed to run between, then the module final blocks aren't really
final.  So for example, any simulation statistics printed out by a
module final block might be invalidated by the further execution before
exiting.

On the other hand, if a program final block did not execute in the
reactive region, this might surprise users and create confusion.

Steven Sharp
sharp@cadence.com