Subject: RE: Minor enhancement request (AMS)
From: Michael McNamara (mac@verisity.com)
Date: Fri Aug 02 2002 - 08:59:31 PDT
Kevin Cameron x3251 writes:
>
> Does anyone have a major objection to adding optional names to continuous
> assign statements e.g.
>
> BNF:
>
> continuous_assign ::== assign [ : label ] [drive strength] [ delay3 ] <list of net assignments>
>
> for instance -
>
> assign : a1 foo = bar;
>
> The reason for wanting this is that multiple continuous assigns to
> the same net are possible in the same module and Verilog-AMS will possibly
> insert a D2A for each, but they are difficult to distinguish if you can't
> name them. D2As are automatically inserted modules that have their instance
> names generated from the signal and process names for debugging, control,
> and hierarchical reference - e.g. "d2a__foo__a1" for the case above.
>
> Regards,
> Kev.
Does
assign foo = a1 (* name=d2a__foo__a1 *) ;
assign foo = a2 (* name=d2a__foo__a2 *) ;
work for you?
1) this is already legal in 1364-2001
2) it seems to be a perfect use of attributes
>
> --
> National Semiconductor
> 2900 Semiconductor Drive, Mail Stop A1-520, Santa Clara, CA 95052-8090
>
>
>
>
>
This archive was generated by hypermail 2b28 : Fri Aug 02 2002 - 09:02:23 PDT