Subject: Re: Minor enhancement request (AMS)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Aug 06 2002 - 11:43:59 PDT
Michael McNamara wrote:
> Kevin Cameron x3251 writes:
> >
> > Does anyone have a major objection to adding optional names to continuous
> > assign statements e.g.
> >
> > BNF:
> >
> > continuous_assign ::== assign [ : label ] [drive strength] [ delay3 ] <list of net assignments>
> >
> > for instance -
> >
> > assign : a1 foo = bar;
> >
> > The reason for wanting this is that multiple continuous assigns to
> > the same net are possible in the same module and Verilog-AMS will possibly
> > insert a D2A for each, but they are difficult to distinguish if you can't
> > name them. D2As are automatically inserted modules that have their instance
> > names generated from the signal and process names for debugging, control,
> > and hierarchical reference - e.g. "d2a__foo__a1" for the case above.
> >
> > Regards,
> > Kev.
>
> Does
> assign foo = a1 (* name=d2a__foo__a1 *) ;
> assign foo = a2 (* name=d2a__foo__a2 *) ;
>
> work for you?
> 1) this is already legal in 1364-2001
> 2) it seems to be a perfect use of attributes
Not really, apart from having to type more everyone would have to agree on the
meaning of the attribute in which case it might as well be a proper part of the
syntax - might do as a stop-gap though :-)
Note: most of the Verilog-AMS issues will become SV issues if folks want to
mix user defined types on a net at some time in the future.
Kev.
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