Subject: Minor enhancement request (AMS)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu Aug 01 2002 - 15:56:13 PDT
Does anyone have a major objection to adding optional names to continuous
assign statements e.g.
BNF:
continuous_assign ::== assign [ : label ] [drive strength] [ delay3 ] <list of net assignments>
for instance -
assign : a1 foo = bar;
The reason for wanting this is that multiple continuous assigns to
the same net are possible in the same module and Verilog-AMS will possibly
insert a D2A for each, but they are difficult to distinguish if you can't
name them. D2As are automatically inserted modules that have their instance
names generated from the signal and process names for debugging, control,
and hierarchical reference - e.g. "d2a__foo__a1" for the case above.
Regards,
Kev.
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