Subject: Re: Minor enhancement request (AMS)
From: Simon Davidmann (simond@co-design.com)
Date: Thu Aug 01 2002 - 16:09:59 PDT
Kevin - your suggestion is inconsistent with existing verilog style - as it
turns the assign keyword into a label
I recommend you suggest requirements and not syntax snippets.... as it is
very hard to get them right unless the whole context of the language is
considered.
fyi I think you already have what you want in systemverilog with:
a1: assign foo = bar;
you just need to the tools to understand that the label refers to the
statement (which it does) and this already works like this in the
definition of assertions.
QED.
Simon
At 03:56 PM 8/1/2002, Kevin Cameron x3251 wrote:
>Does anyone have a major objection to adding optional names to continuous
>assign statements e.g.
>
> BNF:
>
> continuous_assign ::== assign [ : label ] [drive strength] [ delay3 ]
> <list of net assignments>
>
> for instance -
>
> assign : a1 foo = bar;
>
>The reason for wanting this is that multiple continuous assigns to
>the same net are possible in the same module and Verilog-AMS will possibly
>insert a D2A for each, but they are difficult to distinguish if you can't
>name them. D2As are automatically inserted modules that have their instance
>names generated from the signal and process names for debugging, control,
>and hierarchical reference - e.g. "d2a__foo__a1" for the case above.
>
>Regards,
>Kev.
>
>--
>National Semiconductor
>2900 Semiconductor Drive, Mail Stop A1-520, Santa Clara, CA 95052-8090
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