RE: [sv-bc] Verilog Std Ambiguity

From: Daniel Mlynek <daniel.mlynek_at_.....>
Date: Mon Oct 26 2009 - 01:47:10 PDT
Active is same as nc.

DANiel 

-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Steven Sharp
Sent: 22 października 2009 03:16
To: john@svtii.com; sv-bc@server.eda.org; shalom.bresticker@intel.com
Subject: RE: [sv-bc] Verilog Std Ambiguity


>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>Questa seems to behave like Verilog-XL and NC.

It is also possible that VCS and/or Active-HDL behave this way also, if
John's testing was only designed to distinguish between the other two
behaviors.

Steven Sharp
sharp@cadence.com


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Received on Mon Oct 26 01:56:18 2009

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