RE: [sv-bc] Verilog Std Ambiguity

From: Steven Sharp <sharp_at_.....>
Date: Wed Oct 21 2009 - 18:16:11 PDT
>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>Questa seems to behave like Verilog-XL and NC.

It is also possible that VCS and/or Active-HDL behave this way also,
if John's testing was only designed to distinguish between the other
two behaviors.

Steven Sharp
sharp@cadence.com


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