RE: [sv-bc] Verilog Std Ambiguity

No, I can see that VCS is different.

Shalom 

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com] 
> Sent: Thursday, October 22, 2009 3:16 AM
> To: john@svtii.com; sv-bc@eda.org; Bresticker, Shalom
> Subject: RE: [sv-bc] Verilog Std Ambiguity
> 
> 
> >From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> 
> >Questa seems to behave like Verilog-XL and NC.
> 
> It is also possible that VCS and/or Active-HDL behave this way also,
> if John's testing was only designed to distinguish between the other
> two behaviors.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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