>From: "Rich, Dave" <Dave_Rich@mentor.com> >I thought the reasoning behind this wording was a committee compromise, >or a lack of decisiveness, depending on your point of view. > >The default timeunit could be "no timeunit specified". > >This provides an excuse for some implementations producing an error and >some not, and still be conforming to the LRM when there is a mix of >design units with specified and unspecified timeunits. This was completely clear in the 1364-2001 and 1364-2005 standards: "If there is no `timescale specified or it has been reset by a `resetall directive, the time unit and precision are simulator specific. It shall be an error if some modules have a `timescale specified and others do not." The use of the default is clearly different from having a `timescale specified, since it is what is done when no `timescale is specified. Any lack of clarity is the result of rewording to account for the SV extensions, which can specify timeunits without using `timescale. I see no indication of a deliberate change in the rule, and no excuse for ignoring a mix of specified and unspecified timeunits. It doesn't seem like a serious error in a design, though. I could see making it a warning in a tool, especially if you have an option to upgrade it to an error for strict compliance. The biggest problem I see with it is that the rules for determining the global simulation time precision do not account for the possibility of some modules having default precision. But I think that problem also exists if $unit uses default precision, which does not seem to be treated as an error. The obvious answer would be to include that default precision in the determination of the smallest precision in the design. That could lead to further questions in the $unit case. If a $unit without a timeprecision specified could affect the global simulation timeprecision, then you need to define when $unit is considered to exist. For backwards compatibility with Verilog, it seems to me that it must not exist (or must not affect the global timeprecision) in legacy Verilog code with nothing declared outside of a module. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Nov 19 22:35:24 2008
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