> The biggest problem I see with it is that the rules for determining the > global simulation time precision do not account for the possibility of > some modules having default precision. But I think that problem also > exists if $unit uses default precision, which does not seem to be treated > as an error. The obvious answer would be to include that default precision > in the determination of the smallest precision in the design. > > That could lead to further questions in the $unit case. [...] It may be that this could be resolved simply, at the same time fixing a tiresome feature of Verilog that afflicts RTL designers. Many RTL designs contain no non-zero time delays of any kind. It is irksome to be obliged to add a completely redundant timescale/unit/precision to such design files merely to avoid errors from simulators that strictly enforce the "all or none" rule; such a timescale plays no role in the RTL design. If the "all or none" rule were changed to apply not to every design unit, but instead to every #time delay in the elaborated model, then my RTL problem would go away and so, I suspect, would most of the related issues about $unit. (Caveat: there might be some issues about "#time delay"; it's clear, for example, that the #0 syntax in deferred assertions doesn't count as a time delay for the purposes of this argument, and it's not obvious whether #0 and #1step in clocking blocks should either.) -- Jonathan Bromley Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Nov 20 01:35:29 2008
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