RE: [sv-bc] Packed dimension [0:0] - What should happen?

From: Maidment, Matthew R <matthew.r.maidment_at_.....>
Date: Wed Oct 15 2008 - 09:17:23 PDT
The problem I have seen is related to identifiers declared as 1-bit scalars:

  reg foo;

Some tools accept reference to foo as

  foo

and

  foo[0:0]

I believe the latter is an artifact of Verilog-XL. IMO, the latter should not be allowed.
It was a "feature" of Verilog-XL and other tools that were written to comply.
I don't believe it is described in a LRM.


The only other statements I see that might be related to your description are in 6.20.2 of
1800-2009 Draft7 and they list how an untyped parameter can be addressed based on the value to which its assigned.

I'd need to see some code before taking further action-- but maybe Shalom or someone else can decode more from your statements.

Matt
--
Matt Maidment
mmaidmen@ichips.intel.com


>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
>Clifford E. Cummings
>Sent: Wednesday, October 15, 2008 8:44 AM
>To: sv-bc@eda.org
>Cc: sv-ac@eda.org; sv-sc@eda.org
>Subject: [sv-bc] Packed dimension [0:0] - What should happen?
>
>Hi, All -
>
>Question for you regarding packed dimensions that are only one-wide
>
>I seem to recall that Shalom entered a clarification of what should
>happen when a packed dimension resolves to [0:0] after passing
>parameters (I'm not sure if Shalom is on vacation this week due to an
>Israeli holiday or not).
>
>I am teaching a SystemVerilog class this week and this issue has come
>up. The engineers say that some tools are dropping a packed dimension
>that includes [0:0] but that their parameterized code wants to
>reference the packed dimension.
>
>Is there a Mantis item on this or have any of you run into this
>yourself?
>
>Thanks.
>
>Regards - Cliff
>
>----------------------------------------------------
>Cliff Cummings - Sunburst Design, Inc.
>14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>Phone: 503-641-8446 / FAX: 503-641-8486
>cliffc@sunburst-design.com / www.sunburst-design.com
>Expert Verilog, SystemVerilog, Synthesis and Verification Training
>
>
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Received on Wed Oct 15 09:26:26 2008

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