Hi, All - Question for you regarding packed dimensions that are only one-wide I seem to recall that Shalom entered a clarification of what should happen when a packed dimension resolves to [0:0] after passing parameters (I'm not sure if Shalom is on vacation this week due to an Israeli holiday or not). I am teaching a SystemVerilog class this week and this issue has come up. The engineers say that some tools are dropping a packed dimension that includes [0:0] but that their parameterized code wants to reference the packed dimension. Is there a Mantis item on this or have any of you run into this yourself? Thanks. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Oct 15 08:48:07 2008
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