[sv-bc] RE: [sv-sc] Packed dimension [0:0] - What should happen?

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Wed Oct 15 2008 - 08:59:36 PDT
Cliff,

See Mantis 1613.

a[0:0] is a 1-bit vector, not a scalar.

Regards,
Shalom 

> -----Original Message-----
> From: owner-sv-sc@server.eda.org 
> [mailto:owner-sv-sc@server.eda.org] On Behalf Of Clifford E. Cummings
> Sent: Wednesday, October 15, 2008 5:44 PM
> To: sv-bc@server.eda.org
> Cc: sv-ac@server.eda.org; sv-sc@eda.org
> Subject: [sv-sc] Packed dimension [0:0] - What should happen?
> 
> Hi, All -
> 
> Question for you regarding packed dimensions that are only one-wide
> 
> I seem to recall that Shalom entered a clarification of what 
> should happen when a packed dimension resolves to [0:0] after 
> passing parameters (I'm not sure if Shalom is on vacation 
> this week due to an Israeli holiday or not).
> 
> I am teaching a SystemVerilog class this week and this issue 
> has come up. The engineers say that some tools are dropping a 
> packed dimension that includes [0:0] but that their 
> parameterized code wants to reference the packed dimension.
> 
> Is there a Mantis item on this or have any of you run into 
> this yourself?
> 
> Thanks.
> 
> Regards - Cliff
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com Expert 
> Verilog, SystemVerilog, Synthesis and Verification Training
> 
> 
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Received on Wed Oct 15 09:06:21 2008

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