RE: [sv-bc] [sv-ec] module parameter assigned to specify parameter

Hi, 

> Also, it appears that SDF 
> annotation was intended to occur later than normal parameter 
> setting, and be unable to affect the structural details of 
> the design that can be affected by parameters.

The LRM says,
"The keyword specparam declares a special type of parameter that is
intended only for providing timing and delay values, but can appear in
any expression that is not assigned to a parameter and is not part of
the range specification of a declaration."

That still allows specparam to be used in places that affects structural
details of a design. Consider the following:

logic [31:0] q;
specparam S = 1;
wire a = q[S];

or consider a specparam being used as the condition of a generate-if or
generate-case.

The enhancement allowing specparams to be used outside specify blocks
was defined by the old ATF as part of the early Verilog-2001 work. It
seems that the original request was only to allow specparams to be used
in delay contexts, such as #S. This enhancement had been implemented in
Verilog-XL and Cadence wanted the standard to support it.

Regards,
Shalom
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.