I think you have to ask why specparams exist, and why parameters were not allowed to be used in specify blocks instead. I think the answer is that parameters are supposed to be modified from within the Verilog code, while specparams are supposed to be modified through SDF annotation. If you allow the two to be assigned to each other, then it is not clear how the mechanisms would interact. Also, it appears that SDF annotation was intended to occur later than normal parameter setting, and be unable to affect the structural details of the design that can be affected by parameters. So you definitely cannot set a parameter value using a specparam, and there could be problems setting a specparam using a parameter value. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Aug 25 18:55:13 2008
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