RE: [sv-bc] Forward typedef issue

I think the LRM is clear that this should be an error. 

 

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Surya Pratik Saha
Sent: Wednesday, July 16, 2008 1:03 AM
To: sv-bc@eda.org; sv-ec@eda.org
Subject: [sv-bc] Forward typedef issue

 

Hi,
As per SV 1800 LRM (4.9 User-defined types):
The actual type definition of a forward typedef declaration shall be
resolved within the same local scope or generate block.

Now if we consider the following e.g:
module top;
    typedef int myint;
    task t;
        typedef myint;
        myint x;
    endtask
endmodule

Where you can see inside task 't', 'myint' typedef is forward typedef,
but never explicitly declared. But most of the standard simulators pass
the case, taking the definition from module 'top'. What should be the
expected behaviour?



-- 
Regards
Surya


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