Re: [sv-bc] Forward typedef issue

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Wed Jul 16 2008 - 05:40:03 PDT
This should be illegal.  Simulators accepting this would not be LRM
compliant.

Gord


Surya Pratik Saha wrote:
> Hi,
> As per SV 1800 LRM (4.9 User-defined types):
> *The actual type definition of a forward typedef declaration shall be 
> resolved within the same local scope or generate block.
> *
> Now if we consider the following e.g:
> module top;
>     typedef int myint;
>     task t;
>         typedef myint;
>         myint x;
>     endtask
> endmodule
> 
> Where you can see inside task 't', 'myint' typedef is forward typedef, 
> but never explicitly declared. But most of the standard simulators pass 
> the case, taking the definition from module 'top'. What should be the 
> expected behaviour?
> 
> -- 
> Regards
> Surya
> 
> 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Wed Jul 16 05:40:35 2008

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