Re: [sv-bc] 2005: Deferred assertions (new proposal at http://www.verilog.org/mantis/view.php?id=2005)

From: Adam Krolnik <adam.krolnik_at_.....>
Date: Mon Oct 29 2007 - 08:55:41 PDT
Hello all;

My concern with this new syntax is that you are now very close to 
concurrent assertions.

Deferred:
assert  (#0 | event_expr) ...

Concurrent
assert property ...

If you keep the ability for an event expression, then you have two 
seemingly same syntax constructions.
This may cause confusion to users.

SV-AC what do you think about this confusion between deferred and 
concurrent forms ?

-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"




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Received on Mon Oct 29 08:58:38 2007

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