RE: [sv-bc] 2005: Deferred assertions (new proposal at http://www.verilog.org/mantis/view.php?id=2005)

Hi Erik,

The new syntax is intuitive, but I would extend it to allow the forms
like

assert #0 (@clk expr);

The reason of doing that is to be able to use (degenerate) sequences to
specify the assertion body. This will allow building assertion libraries
for boolean assertions. E.g.,

sequence same(a, b, rst, clk)
    @clk rst || a == b;
endsequence : same

assert #0 (same(x, y, 0, posedge clk));

If only syntax

assert @clk (expr);

is permitted, it will be difficult to build libraries of these
assertions.

Minor comment. In the Motivation section "Postponed" should be
capitalized.

Regards,
Dmitry

-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Seligman, Erik
Sent: Saturday, October 27, 2007 12:19 AM
To: sv-ac@server.eda.org
Cc: sv-bc@server.eda-stds.org
Subject: [sv-bc] 2005: Deferred assertions (new proposal at
http://www.verilog.org/mantis/view.php?id=2005)


Hi all--

I've revised the draft, based on suggestions from Dmitry, Doug, and a
few others.  The major changes:
- Rather than a new keyword, used the suggestion of 'assert #0'
suggested by Doug.  Tell me if everyone thinks this is OK, or if it
seems confusing & we should add a keyword after all.  
- Added optional event control for deferred assertions.  Doug-- tell me
if what I put in there sounds like what you had in mind.  I think a
followup email with details was implied by your last one, but I didn't
find it in my inbox.  I thought this sounded useful for some cases.
- Added implicit always_comb for deferred asserts outside procedural
code. 
- Added more examples.

Anyway, the new draft is attached (and added to the Mantis), with
changes marked.  As before, tell me if you have major objections, or
suggested improvements.  Thanks!

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