Re: [sv-bc] structure literal example in standard

Please review Shalom's proposal for Mantis item 1666.  A copy of the
proposal is attached.

Personally, I'm concerned about the proposed nondeterminism.

   "Implementations may evaluate assignment patterns before
replication."

I think this should be 'shall'.  

Compare these rules from 5.1.14 and 9.5 in Verilog-2005 --

   "When a replication expression is evaluated, the operands shall be
evaluated
    exactly once, even if the replication constant is zero."

   "The case expression given in parentheses shall be evaluated exactly
once and 
    before any of the case item expressions."

-- Brad