RE: [sv-bc] Re: [sv-ec] List of port expressions

Brad,

Thanks for the references, which back up what I was saying.

This shows that this type of port definition is available in non-ANSI
port declarations.

I agree that the 1364-2005 12.3.3 examples are not clear enough.

One confusion is that the examples which follow the first example use
the same port/signal names as the first example, which can mislead one
to think that they are based on the same declarations as in the first
example, and this is not so.


>        module renamed_concat (.a({b,c}), f, .g(h[1]));
>               // Names 'b', 'c', 'f', 'h' are defined inside the
module.
>               // Names 'a', 'f', 'g' are defined for port connections.
>               // Can use named port connections.
> 
> How is h "defined inside the module"?  According to the BNF, h must be
a
> port_identifier, so presumably it must be something like
> 
>              output [3:0] h;

[SB] Yes, and that is also confusing because really only h[1] is an
output and the other bits are internal only.

> 
> That restriction would make no sense for the 2001-style port
> declarations, because, in the 2001 style, ports cannot be defined
inside
> the module.
> 
>    module mymod (
>      output .P1(r[3:0]),
>      output .P2(r[7:4]),
>      ref .Y(x),
>      input bit R );
> 
>      logic [7:0] r;
>      int x;
>      ...
>    endmodule

[SB] I do not agree that the ports are not 'defined inside' the module. 
I think that statement (which I agree is unclear) means 'visible
inside'. 

Take the following example, which also appears there:

module complex_ports ({c,d}, .e(f));
  // Nets {c,d} receive the first port bits.
  // Name 'f' is declared inside the module.
  // Name 'e' is defined outside the module.

There is no declaration of e anywhere. The statement that 'e is defined
outside the module' means that the name e is used when referencing the
port from outside the module, i.e., in a module instance port connection
list, whereas inside the module you can only see f, but not e.

Where I do see a problem is that in the non-ANSI syntax, the port
declarations (input, output, inout) refer to the internal signals. Here
in the SV ANSI syntax, it looks like the port declarations refer to the
port names themselves (P1, P2, Y). I say this because the SV example
shows additional declarations of the internal signals (r,x) and one of
the principles of the ANSI-style declaration is that the entire
declaration is found in one place, in the module header, and not split
between several statements.

This 1800 syntax looks to me to be inconsistent with 1364.

Would it be legal to write

   module mymod (
      output .P1(r[3:0]),
      input .P2(r[7:4]),
      ...                     ?

Shalom