Date: Mon May 01 2006 - 01:42:31 PDT
6.3 says, "Constants are named data variables that never change. Verilog provides three constructs for defining elaboration-time constants: the parameter, localparam and specparam declarations." This looks a little strange. I understand that in 6.3.5, one might want to think of consts as a special type of variable, but it seems strange to say that a parameter is a variable, even if one that never changes. In what way is it a variable? Even its declaration differs from that of variables. Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 I don't represent Intel
