RE: [sv-bc] compiler directives in middle of statement

The following are 'interesting' cases:

- sv, unlike Verilog, allows all sorts of code outside modules. 

- The following directives don't say they are restricted to being
outside modules: `celldefine, `timescale

- `pragma

- `pragma protect


Shalom


> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Wednesday, January 04, 2006 2:16 AM
> To: sv-bc@eda.org; Bresticker, Shalom
> Subject: Re: [sv-bc] compiler directives in middle of statement
> 
> The LRM restricts some compiler directives to specific places,
> such as
> outside of modules (generally because they are intended to
> apply to an
> entire module, and it would be confusing if they changed in the
> middle
> of the module).  Aside from those, I think compiler directives
> are
> allowed anywhere you like, including in the middle of
> statements.
> 
> The simulators I have access to have no problem with a macro
> definition
> in the middle of a continuous assignment.
> 
> Steven Sharp
> sharp@cadence.com