Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

Brad,

This is not correct.

In typical one-hot logic, we don't care if there is a small glitch when
going from one value to another, since the output value is only sampled
on the clock edge, and the glitch is so short that we don't care.
But the glitch can indeed exist.

If I write

casez(a[1:0]) //synthesis parallel_case
2'b1?: out = b;
2'b?1: out = c;
endcase

I indeed tell the synthesizer to assume that the cases are
mutually exclusive, but I don't assume that the 2'b11 cannot occur as a
transient.

Shalom

On Tue, 9 Nov 2004, Brad Pierce wrote:

> The user is asking for hardware that takes advantage of his/her assertion.
> So 'unique' should be a promise that the implicit selector signals
> will be one-hot by the end of each simulation time step.

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
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