Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

From: Brad Pierce <Brad.Pierce@synopsys.com>
Date: Tue Nov 09 2004 - 18:21:10 PST

We can't assume synchronous logic. And 'unique' should be a
stronger assertion than that anyway.

The user is asking for hardware that takes advantage of his/her assertion.
So 'unique' should be a promise that the implicit selector signals
will be one-hot by the end of each simulation time step.

In the Postponed region, for each unique case/if statement, check
whether its last evaluation (if any) during the current time step
detected a violation. If so, issue an error.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Neil
Korpusik
Sent: Tuesday, November 09, 2004 12:36 PM
To: Greg Jaxon
Cc: Steven Sharp; sv-bc@eda.org; Brad.Pierce@synopsys.COM
Subject: Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent
use of error and warning

Greg Jaxon wrote:

> The way I view "unique" is this: synthesis is going to assume that it
> has a one-hot set of signals driving some selectors. The user would like
confirmation
> that this (derived) signal set is indeed one-hot over some time intervals.
> A simulation compiler should help him construct that assertion and test it
throughout
> the relevant time period. I realize that pinning down what this means is
> the heart of the matter, and I am personally not a bit savvy about
simulation,
> so I cannot do it. What do users do now to get simulators to check their
> "parallel case / full case" directives?

All of the formal tools that we have used perform such checks at the active
clock edge.
This includes simulation monitors as well. In general, such checks only need
to hold
true at the clock edge.

Is there some bullet-proof recipe
> for adding checks that we can standardize? Failing that, is there
anything
> close enough?

--
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Neil Korpusik                                     Tel: 408-720-4852
Member of Technical Staff                         Fax: 408-720-4850
Frontend Technologies - ASICs & Processors (FTAP)
Sun Microsystems
email: neil.korpusik@sun.com
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Received on Tue Nov 9 18:20:25 2004

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