Greg Jaxon wrote:
> The way I view "unique" is this: synthesis is going to assume that it
> has a one-hot set of signals driving some selectors. The user would like confirmation
> that this (derived) signal set is indeed one-hot over some time intervals.
> A simulation compiler should help him construct that assertion and test it throughout
> the relevant time period. I realize that pinning down what this means is
> the heart of the matter, and I am personally not a bit savvy about simulation,
> so I cannot do it. What do users do now to get simulators to check their
> "parallel case / full case" directives?
All of the formal tools that we have used perform such checks at the active clock edge.
This includes simulation monitors as well. In general, such checks only need to hold
true at the clock edge.
Is there some bullet-proof recipe
> for adding checks that we can standardize? Failing that, is there anything
> close enough?
-- --------------------------------------------------------------------- Neil Korpusik Tel: 408-720-4852 Member of Technical Staff Fax: 408-720-4850 Frontend Technologies - ASICs & Processors (FTAP) Sun Microsystems email: neil.korpusik@sun.com ---------------------------------------------------------------------Received on Tue Nov 9 12:36:41 2004
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