[sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

From: Stuart Sutherland <stuart@sutherland-hdl.com>
Date: Wed Sep 01 2004 - 23:17:55 PDT

Section 18.4, Selection Statements

The description of unique if says "A software tool shall issue an error if
it determines that more than one condition is, or can be, true."

The description of unique case says "shall issue a warning message if more
than one case item matches the case expression."

The inconsistency of error versus warning does not make sense. These should
both be warnings or both be errors.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062

Sutherland HDL, Inc. -- Training Engineers to be Verilog, SystemVerilog
and VHDL Wizards! http://www.sutherland-hdl.com
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Received on Wed Sep 1 23:18:42 2004

This archive was generated by hypermail 2.1.8 : Wed Sep 01 2004 - 23:19:00 PDT