Re: [sv-bc] ref port and interface prt declaration questions

Françoise,

 From 18.12.1 "A ref port shall be connected to an equivalent variable
data type. References to the port variable shall be
treated as hierarchal references to the variable it is connected to in
its instantiation. This kind of port cannot
be left unconnected. See Section 5.8.1, Equivalent types."

As with all arrays in Verilog, it is the shape of the array, not the
actual ranges that matter.

Dave

Francoise Martinolle wrote:

> When using a ref port in a module declaration, do I need to have the
> exact same data type
> as for the actual declaration it points to? or are they some special
> connections rules between the array of pointers in module M below and
> the array declaration in module TOP.
>
> If the example below is legal, the rules should be specified.
>
> ex:
>
> module TOP;
> reg b [2:1][2:4];
>
> M u1 (b);
> endmodule
>
> Do I have to declare :
> module M (ref reg r [2:1] [2:4]); // same ranges, same size but
> different port name
>
> endmodule
>
>
> or is the following different ref declaration legal?
> module M (ref reg r [1:0] [2:0]); // note different ranges and ort
> name, but same size
>
> endmodule
>
> Same question for interfaces:
>
> module TOP;
> I myi[1:0](); // instantiate an array of 2 interfaces
>
> M u1( myi); // pass the entire array of interfaces
> endmodule
>
> module M (interface bus [2:1]); // use generic interface
>
> endmodule
>
> module M (I [2:1]); // use specific interface I
>
> endmodule
>
>

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