[sv-bc] Modport definitions

Good morning;

Is it possible to declare a port in a modport to be a subset (part selection)
of the full port? It is common to see a module using a subset of the bits
of a signal (both as inputs and outputs.)

I see that one can provide a port expression ( .port_name(expression) ), but don't know
if this is the way to do it.

    Thanks.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion Based Design"
Received on Mon Mar 8 12:20:37 2004