Re: [sv-bc] Interconnect?

From: Greg Jaxon <Greg.Jaxon@synopsys.com>
Date: Tue Aug 06 2013 - 14:30:50 PDT
Thanks for the road map document!
My recollection of the ANSI style port rules (pages 667-9) included various special cases for interface, the new exceptions for interconnect tricked my eyes.
~ never mind ~ :~)

-g-

On 8/5/2013 6:49 PM, "Brad Pierce" wrote:

Hi Greg,

 

The 'interconnect' keyword is new in SV12, for generic (typeless) nets and ports, and is used for discrete real modeling. In digital synthesis, we just treat it like 'wire'. For context, see attached. There are also user-defined resolution functions with the new ‘nettype’ keyword which is not yet supported in digital synthesis.

 

-- Brad

 



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