RE: [sv-bc] Interconnect?

We discussed improving the port rules by, among other things, adding references to interfaces, and I started work on it, but dropped it as there did not seem to be sufficient interest in the committee. Maybe next time...

Shalom

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Greg Jaxon
Sent: Wednesday, August 07, 2013 00:31
To: Brad Pierce
Cc: SV_BC List
Subject: Re: [sv-bc] Interconnect?

Thanks for the road map document!
My recollection of the ANSI style port rules (pages 667-9) included various special cases for interface, the new exceptions for interconnect tricked my eyes.
~ never mind ~ :~)

-g-

On 8/5/2013 6:49 PM, "Brad Pierce" wrote:

Hi Greg,



The 'interconnect' keyword is new in SV12, for generic (typeless) nets and ports, and is used for discrete real modeling. In digital synthesis, we just treat it like 'wire'. For context, see attached. There are also user-defined resolution functions with the new 'nettype' keyword which is not yet supported in digital synthesis.



-- Brad




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