Subject: RE: [sv-bc] RE: [sv-ec] Question: logic & reg - what is the diffe rence?
From: Srouji, Johny (johny.srouji@intel.com)
Date: Sun Jun 08 2003 - 00:48:37 PDT
Hi All,
Jay is right. Attached are the minutes from that meeting. It includes
the details of the discussion and our decisions.
Hope this clarifies this topic.
--- Johny.
-----Original Message-----
From: Jay Lawrence [mailto:lawrence@cadence.com]
Sent: Thursday, June 05, 2003 10:48 PM
To: Clifford E. Cummings; sv-ec@eda.org; sv-bc@eda.org
Subject: RE: [sv-bc] RE: [sv-ec] Question: logic & reg - what is the
difference?
We did resolve that the new rules for continuous assignments being
allowed to variables applied to ALL variables. This simplification made
logic and reg identical. We even had a straw vote on eliminating logic
because it was now redundant. We then paused in our rush to judgement
because logic can be declared inside other things (like a struct) and
maybe we wanted to use 'logic' as purely a name for a type and leave
'reg' as the declaration of an object.
Jay
P.s. The "data type donation" to IEEE does exactly this. It leaves reg
as an object declaration and logic as a type.
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com]
> Sent: Thursday, June 05, 2003 6:49 AM
> To: sv-ec@eda.org; sv-bc@eda.org
> Subject: [sv-bc] RE: [sv-ec] Question: logic & reg - what is
> the difference?
>
>
> At 07:02 PM 6/4/03 -0700, Andy Tsay wrote:
> >Hi,
> >
> >It seems the only difference is:
> >a logic object can be used for both continuous and
> >procedural assignment, but a reg object can only be in
> >a procedural assignment.
> >
> >A logic object can be used as output of a gate, but a
> >reg object cannot.
>
> This is what I thought too, but this is not what it says in
> section 5.6.
>
>
> >-- Andy
> >
> >
> >--- "David W. Smith" <david.smith@synopsys.com> wrote:
> > > Cliff,
> > >
> > > I seem to remember the meeting, and the vote, where
> > > it was decided that
> > > logic and reg where the same thing. I think you were
> > > there. It appears that
> > > some text in the LRM may not have been caught when
> > > BC made the change.
> > >
> > > Since this was all done in the BC I will forward it
> > > to BC for comment.
>
> Thanks, David. I was at the face-to-face meeting in San Jose and a
> follow-on phone meeting when we discussed logic and some
> potential behavior
> surrounding regs but I did not remember this change. I was
> wondering if the
> EC had "enhanced" the definition of regs. It is beginning to
> look like a
> significant bug in the spec (especially if ModelTech is
> reading what I am
> reading and attempting to implement the bug).
>
> Regards - Cliff
>
> > >
> > > Regards
> > > David
> > >
> > > David W. Smith
> > > Synopsys Scientist
> > >
> > > Synopsys, Inc.
> > > Synopsys Technology Park
> > > 2025 NW Cornelius Pass Road
> > > Hillsboro, OR 97124
> > >
> > > Voice: 503.547.6467
> > > Main: 503.547.6000
> > > FAX: 503.547.6906
> > > Email: david.smith@synopsys.com
> > > http://www.synopsys.com
> > >
> > >
> > >
> > > -----Original Message-----
> > > From: owner-sv-ec@eda.org
> > > [mailto:owner-sv-ec@eda.org] On Behalf Of Clifford
> > > E. Cummings
> > > Sent: Wednesday, June 04, 2003 3:37 PM
> > > To: sv-ec@eda.org
> > > Subject: [sv-ec] Question: logic & reg - what is the
> > > difference?
> > >
> > >
> > > Hi, all -
> > >
> > > I was talking to the ModelSim developers and we ran
> > > into this question:
> > >
> > > Are logic and reg the same thing? Did I miss this
> > > proposal and vote?
> > >
> > > According to table 3.1, logic has "different use
> > > rules from reg."
> > >
> > > Section 5.6 - 3rd paragraph
> > >
> > > In SystemVerilog, all variables (including reg?) can
> > > now be written either
> > > by one continuous assignment, or by one or more
> > > procedural statements,
> > > including procedural continuous assignments. It
> > > shall be an error to have
> > > multiple continuous assignments or a mixture of
> > > procedural and continuous
> > > assignments writing to the same variable. All data
> > > types can write through
> > > a port.
> > >
> > > So now what is the difference between a logic and a
> > > reg?
> > >
> > > Is logic 100% redundant with reg? Both must be
> > > declared.
> > >
> > > Regards - Cliff
> > > ----------------------------------------------------
> > > Cliff Cummings - Sunburst Design, Inc.
> > > 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> > > Phone: 503-641-8446 / FAX: 503-641-8486
> > > cliffc@sunburst-design.com /
> > > www.sunburst-design.com Expert Verilog, Synthesis
> > > and Verification Training
> > >
> > >
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
>
>
>
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