[sv-bc] EE Times Article about IEEE meeting at DAC


Subject: [sv-bc] EE Times Article about IEEE meeting at DAC
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Jun 06 2003 - 19:28:01 PDT


Hi, all -

You may have read the article: "IEEE forum attendees support SystemVerilog"
on the EE Times web site:

http://www.eedesign.com/news/OEG20030603S0048

That article included the following unfortunately positioned quotes:

"Others started to question whether all of SystemVerilog 3.1 will sail
through the IEEE. "Just because we're bringing in SystemVerilog doesn't
mean we're rubber-stamping it," said consultant Cliff Cummings. "I can't
imagine the Vera stuff will go into the IEEE standard," said Baty. The
Synopsys Vera language is the basis of some testbench constructs in
SystemVerilog 3.1."

For the record, when we were asked for enhancement requests, I was the one
that put SystemVerilog 3.1 at the top of the list, right under Kurt Baty's
request for floating point standardization. Then I made the point that it
would not be rubber stamped.

Near the end of the meeting, Kurt made his comment about Vera not being
part of IEEE Verilog, but Richard failed to report my immediate response
that I believed IT WOULD INDEED be part of IEEE Verilog.

Unfortunately, our two quotes in isolation make it appear that we were
opposed to SystemVerilog being added to IEEE Verilog, which was not even
near to the actual sentiment of the meeting. Other attendees included
Arturo Salz, Dave Kelf, Phil Moorby, Dave Rich, Tom Fitzpatrick, Jay
Lawrence, Stu Sutherland and others from the SystemVerilog committees. I
believe they will vouch for the fact that the meeting was very positive and
that SystemVerilog was well supported by those in attendance.

When you read the EE Times article, keep this in mind. SystemVerilog
enhancements to IEEE Verilog were, in my opinion, very well received.

The only other amusing part of the meeting was when Kurt asked, "is there
any other enhancement idea that can be salvaged from VHDL" or have we
already extracted all of the good stuff and added it to Verilog. I was sure
that Richard Goering was going to quote Kurt in EE Times and stir up
another firestorm!

Regards - Cliff Cummings

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training



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