Subject: [sv-bc] Re: [sv-ec] logic -vs- ulogic
From: Simon Davidmann (simon@his-home.demon.co.uk)
Date: Mon Apr 14 2003 - 14:44:44 PDT
I think that it is irrelevant if VHDL has keywords like logic that behave
in different ways to what is proposed with SystemVerilog (after all VHDL is
a dead language :-) ) - the key thing about SystemVerilog is that it is
consistent in itself and not other languages.
if we add prefix in front of keywords - then we should do it consistently
across all of Verilog
for example
wires should become res_wires to show they are resolved
regs should be unr_reg to show they are not etc
and then I would agree about putting prefixes in front of logic and bit
we need to ensure that as a language SystemVerilog works and is clean and
not waste time on silly things like fiddling with keywords - we have far
more fundamental things to concern ourselves with.
I suggest we leave keywords like logic and bit alone - they fit with
Verilog style...
Simon
At 06:12 PM 4/14/2003, Steven Sharp wrote:
>I agree that the names should be changed to something less likely to cause
>conflicts. I am not sure that "ulogic" and "ubit" are the best choices.
>The "u" might imply unsigned instead of unresolved, to many people. And if
>wires of these types are allowed, they won't necessarily be unresolved.
>Multiple drivers could be allowed. The resolution function for "logic" is
>obvious, and "bit" could use wire-AND or wire-OR.
>
>Steven Sharp
>sharp@cadence.com
This archive was generated by hypermail 2b28 : Mon Apr 14 2003 - 14:45:34 PDT