Subject: [sv-bc] When did the SV-BC vote on "ulogic?"
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Apr 14 2003 - 10:22:46 PDT
Hi, All -
David tells me that the SV-BC already voted on logic -vs- ulogic. Could
somebody help point me to the minutes or documentation that shows we voted
on this (it probably happened when I missed a meeting).
Regards - Cliff
Cliff Cummings - SystemVerilog 3.1-Draft 4 Review
First: I would again like to propose that "logic" be renamed to "ulogic"
and "bit" be renamed to "ubit." This has had some support in the committees.
The latter names are less likely to appear as identifiers in existing
models, plus, ulogic and ubit are unresolved, so the naming convention is
more consistent for anyone with a VHDL background looking to adopt
SystemVerilog. VHDL-types are going to think "logic" and "bit" are resolved
types (ala std_logic & std_bit), which they are not.
DWS: This is not the place to make a change like this. Your committee has
already voted on it and it is closed.
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Cliff Cummings - Sunburst Design, Inc.
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