Subject: Re: [sv-bc] When did the SV-BC vote on "ulogic?"
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Apr 14 2003 - 11:16:53 PDT
Cliff,
There were a series of straw polls for SV-BC18h,i on the Jan 22 F2F BC
meeting that prompted you to file this with the EC
http://www.eda.org/sv-bc/hm/att-0379/01-03-01-22_minutes.txt
The final vote for 18h,i was recoreded in
http://www.eda.org/sv-bc/hm/att-0516/02-03_02_24.txt
Dave
Clifford E. Cummings wrote:
> Hi, All -
>
> David tells me that the SV-BC already voted on logic -vs- ulogic.
> Could somebody help point me to the minutes or documentation that
> shows we voted on this (it probably happened when I missed a meeting).
>
> Regards - Cliff
>
> Cliff Cummings - SystemVerilog 3.1-Draft 4 Review
>
> First: I would again like to propose that "logic" be renamed to
> "ulogic" and "bit" be renamed to "ubit." This has had some support in
> the committees.
>
> The latter names are less likely to appear as identifiers in existing
> models, plus, ulogic and ubit are unresolved, so the naming convention
> is more consistent for anyone with a VHDL background looking to adopt
> SystemVerilog. VHDL-types are going to think "logic" and "bit" are
> resolved types (ala std_logic & std_bit), which they are not.
>
> DWS: This is not the place to make a change like this. Your committee
> has already voted on it and it is closed.
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
>
>
>
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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