RE: [sv-ec] Are procedural assignments to nets now legal?

Hi Gord,

I found this code in an earlier version of the proposal. I believe this is correct. Do you agree?

<file driver.svr>
module driver import NetsPkg::*;
              #(parameter int delay = 30,
                          int iterations = 256)
               (output realNet [0:1] out);
  timeunit 1ns / 1ps;
  real outR[1:0];

  assign out = outR;

  initial begin
    outR[0] = 0.0;
    outR[1] = 3.3;
    for (int i = 0; i < iterations; i++)
      #delay outR[0] += 0.2;
             outR[1] -= 0.2;
  end
endmodule : driver

Thanks,
Scott

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Gordon Vreugdenhil
Sent: Tuesday, January 31, 2012 1:53 PM
To: Stuart Sutherland
Cc: sv-dc@eda-stds.org; sv-ec@eda-stds.org
Subject: Re: [sv-ec] Are procedural assignments to nets now legal?

No, procedural assignments to nets (including a nettype) are not legal. The example is
not legal and should be fixed.

Gord.

On 1/31/2012 1:38 PM, Stuart Sutherland wrote:
Clause 6.6.8 of P1800-2012 Draft 4 (added in draft 3 by Mantis 3724) has an example of defining a new nettype:

nettype real realNet;

And then doing procedural assignments to that net. This is in the first driver module in the second example of 6.6.8.

Is it now legal to make procedural assignments to nets? If so, what Mantis item added that feature?

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
www.sutherland-hdl.com<http://www.sutherland-hdl.com>

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