RE: [sv-ec] {}

> There still needs to be a normative footnote in Annex A
> pointing out that {} is legal only as a UAC.... unless
> there's a desire to permit empty concatenations.

Yes, null concatenations would be a major enhancement, something to consider in SystemVerilog 2012, perhaps in combination with parameterized subroutines.

-- Brad

________________________________________
From: owner-sv-ec@eda.org [owner-sv-ec@eda.org] On Behalf Of jonathan.bromley@doulos.com [jonathan.bromley@doulos.com]
Sent: Tuesday, July 28, 2009 1:35 PM
To: Bresticker, Shalom
Cc: sv-ec@server.eda.org
Subject: RE: [sv-ec] {}

> Is it agreed that empty unpacked array concatenations were to be
allowed?

I don't know about "agreed", but there's absolutely no doubt
in my mind that it should be legal and should denote an array
with no elements.  I don't see any difficulty here.  UACs
are valid only as the source in an assignment-like context.
If the target is a variable-sized array, then it can have
a zero-length array assigned to it.  If the target is a
fixed-size array, then the zero-length source UAC must
inevitably be an error since its size is sure to be
different from that of any possible fixed-size array.

I've raised Mantis 2831.

There still needs to be a normative footnote in Annex A
pointing out that {} is legal only as a UAC.... unless
there's a desire to permit empty concatenations.  I can
imagine the latter might, just possibly, be useful in
the same way that null array slices are useful in VHDL.
--
Jonathan Bromley
Consultant

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