Hi, All - I think random falls under EC, so at the bottom is the question. I was playing with $urandom and trying to seed it, and have run into problems related to my understanding of seeding this function. The following code is also in an attached file: urandomtest.sv (I run the nine different iterations using +define+RUN1 thru +define+RUN9) program urandomtest; logic [7:0] a; int seed; initial $monitor("a=%h", a); initial begin `ifdef RUN1 repeat(20) #1 a = $random(); `elsif RUN2 repeat(20) #1 a = $random(145); `elsif RUN3 seed = 145; repeat(20) #1 a = $random(seed); `elsif RUN4 repeat(20) #1 a = $urandom(); `elsif RUN5 repeat(20) #1 a = $urandom(145); `elsif RUN6 seed = 145; repeat(20) #1 a = $urandom(seed); `elsif RUN7 repeat(20) #1 a = $urandom_range(145); `elsif RUN8 repeat(20) #1 a = $urandom_range(100,145); `elsif RUN9 seed = 145; repeat(20) #1 a = $urandom_range(seed); `endif end endprogram $random - normal Verilog behavior RUN1 - $random() generates 20 random numbers RUN2 - generates the same random number 20 times, each time using the seed value of 145. RUN3 - generates 20 random numbers with the first number based on the "seed" value of 145. $urandom - a few surprises RUN4 - generates 20 urandom numbers. RUN5 - generates the same urandom number 20 times, each time using the seed value of 145. In P1800-2009 Ballot Draft, clause 18.13.1, last sentence in the paragraph after the prototype function is a little misleading when it says: "The random number generator (RNG) shall generate the same sequence of random numbers every time the same seed is used." RUN6 - generates the same urandom number 20 times, each time using the seed value of 145 (seeding behavior is different than Verilog's $random from RUN3). $urandom_range - no big surprises RUN7 - generates 20 urandom_range numbers between 0-145 RUN8 - generates 20 urandom_range numbers between 100-145 RUN9 - generates 20 urandom_range numbers between 0-145 Question - what is the correct way to seed the $urandom function when used in procedural code outside of a class?? Thanks for any feedback. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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