>As Gord says, the original intent was that they had to be identical. According to 6.9 of IEEE Std 1800-2005 -- "SystemVerilog does not require a category for identical types to be defined here because there is no construct in the SystemVerilog language that requires it. For example, as defined below, int can be interchanged with bit signed [31:0] wherever it is syntactically legal to do so. Users can define their own level of type identity by using the $typename system function (see 22.2) or through use of the PLI." -- Brad -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jul 10 14:57:12 2008
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