RE: [sv-ec] static members of modules

From: Rich, Dave <Dave_Rich_at_.....>
Date: Sat Dec 15 2007 - 04:40:21 PST
The default is static, so the keyword is redundant. 

 

The behavior of a static variable declared a the module level should
match one declared in a block, and that is each module instance creates
a copy of all static members. I will explain the problem with type
compatibility when I answer your other e-mail.

 

Dave

 

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of danielm
Sent: Friday, December 14, 2007 8:19 AM
To: sv-ec@server.eda.org
Subject: [sv-ec] static members of modules

 

SV allows to declare module member as static but doesn't define
behaviour of such static member. Maybe this static keyword is just
redundand(in this case this possibility should be removed from LRM) or
maybe it may have sense - example:

	module sub;

	    static int i ;

	    initial $monitor("%m:: %t> %d", $time, i);

	endmodule

	 

	module top;

	    sub i1();

	    sub i2();

	    initial begin

	          #1;i1.i=1;

	          #1;i2.i=2;

	          #1;

	        $finish;

	    end

	endmodule

Proposition : Variable i should be really static - the same in all
instances - otherwise this use of static is misleading. 

Below 2 possible results which should be ok 1st for 'i' as real static
var and 2nd for 'i' as usual module member:

 

1st

top.i1::                    0>           0
top.i2::                    0>           0

top.i1::                    1>           1

top.i2::                    1>           1

top.i1::                    2>           2

top.i2::                    2>           2

 

2nd

top.i1::                    0>           0
top.i2::                    0>           0

top.i1::                    1>           1

top.i2::                    2>           2

 

 

Daniel Mlynek


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Received on Sat Dec 15 05:17:30 2007

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