RE: [sv-ec] static members of modules

By default all variables in a module are static. Static in a module and
static in class do not mean the same thing. 

________________________________

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
danielm
Sent: Friday, December 14, 2007 8:19 AM
To: sv-ec@eda.org
Subject: [sv-ec] static members of modules


SV allows to declare module member as static but doesn't define
behaviour of such static member. Maybe this static keyword is just
redundand(in this case this possibility should be removed from LRM) or
maybe it may have sense - example:

	module sub;
	    static int i ;
	    initial $monitor("%m:: %t> %d", $time, i);
	endmodule
	 
	module top;
	    sub i1();
	
	    sub i2();
	    initial begin
	          #1;i1.i=1;
	
	          #1;i2.i=2;
	
	          #1;
	        $finish;
	    end
	endmodule

Proposition : Variable i should be really static - the same in all
instances - otherwise this use of static is misleading. 
Below 2 possible results which should be ok 1st for 'i' as real static
var and 2nd for 'i' as usual module member:
 
1st
top.i1::                    0>           0
top.i2::                    0>           0
top.i1::                    1>           1
top.i2::                    1>           1
top.i1::                    2>           2
top.i2::                    2>           2
 
2nd
top.i1::                    0>           0
top.i2::                    0>           0
top.i1::                    1>           1
top.i2::                    2>           2
 
 
Daniel Mlynek

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