re. 1715, Cliff pointed out... I'm not sure what it means to pass a clocking block name through a port or why it is useful. I would like to talk about this in committee meeting. I had simply assumed that it is OK to have a port of "ref event" type, and that's what I meant by "pass through a port" - I agree the phrase is not precise enough. But this raises a question: I can't find anywhere in the LRM that forbids ports of type "ref event"; the BNF definitely admits it, though of course that is not very strong evidence. The little example below works in at least one simulator, with either "ref" or "input" direction; another simulator reports both cases as an error. Is it illegal? module evmod(ref event e); always @e $display("e @%0d", $time); endmodule module top; event E; evmod inst(E); initial #5 ->E; endmodule -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Oct 25 10:00:58 2007
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