Jonathan, A couple responses below. Thanks again for the detailed comments. All, Should I incorporate Jonathan's comments that I marked "OK" into a draft 6 before we do a group review of the proposal? Or would you prefer to review Jonathan's comments one-by-one in the next meeting before I incorporate them? We might save time by having me directly handle the straightforward ones. Thanks, Doug > -----Original Message----- > From: Jonathan Bromley [mailto:jonathan.bromley@doulos.com] > Sent: Monday, February 12, 2007 5:34 AM > To: Warmke, Doug; sv-ec@server.eda.org > Subject: RE: [sv-ec] Comments on 890-5.pdf > > A few comments on the 890-5 proposals relating to > program blocks (clause 16): > > > General comments > ~~~~~~~~~~~~~~~~ > > (1) Design variables > It seems to me that there's some verbal struggling with > the notion of "design variables" or "design signals", with > the phrase requiring glossing each time it's used. Then, > for brevity, we have "design signals in a module" when > strictly we should speak of a module or interface. > Would it be sensible to define the phrase "design signal" > or "design object" at the outset to be a net or variable > declared in a module or interface? DOUG: OK - good idea > > (2) Spelling of "Observed" region name throughout. DOUG: OK > > > 16.3 Eliminating testbench races > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > (1) Wrong font in the paragraph heading. DOUG: OK > > (2) First complete paragraph at the top of page 8 of > 890-5.pdf, third line, just after the new insertion: > it's not clear to me why the use of input #0 is > necessary or relevant here. It might, however, > be useful to observe (in a Note) that a program reading > design signals without using a clocking block will see > the same values as it would if the signals were clocking > inputs with a skew of #0, unless the program then > modifies those signals itself in the same timeslot. DOUG: Good question about the #0. Arturo - care to elaborate on that? Or should we remove the #0? I don't really understand the suggestion for a note. A program without a clocking block will behave completely differently than one with a clocking block, due to the edge-based sampling. I tend to think we could forego the Note suggested here - to be clear, it might get pretty wordy. Thanks again, Doug > > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, > Hampshire, BH24 1AW, UK > Tel: +44 (0)1425 471223 Email: > jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Feb 12 09:48:43 2007
This archive was generated by hypermail 2.1.8 : Mon Feb 12 2007 - 09:49:02 PST