RE: [sv-ec] Multiple triggering of assertions and clockings

Arturo, thanks for your response.

> Forbidding multiple clock triggers in the same time slot does not
> disallow the methodology you suggest: untimed functional 
> models that may
> trigger additional activity in the DUT as part of the Reactive
> processing. Multiple delta-cycles involving the 
> Active/Reactive regions
> is the way SystemVerilog is intended to work when Reactive processes
> post events with no delay to which Active processes are 
> sensitive. This
> means that any signal, including a clock could be triggered 
> from within a Reactive process.

Yes, agreed and understood - except that it *does* disallow
"the methodology I suggest"....

> What we are trying to forbid is *the same* clock signal being 
> triggered more than once in the same time slot. 

An untimed functional model that exhibits ordering of behaviour 
may have a zero-delay "clock".  In particular, assertions 
over such ordered behaviour cannot be expressed without
some clock.

> Remember 

I had failed to remember :-(

> clocking blocks and assertions both
> sample their inputs in the Preponed (or previous Postponed) region,
> hence, if their clocks were to trigger more than once in the same time
> slot, the sampled values would not change.

OK, that's the fundamental reason why what I suggested could never
work.  In Specman, assertions use values sampled at the beginning of
the Specman "tick" which, loosely, corresponds to one complete visit
to the Reactive region set (possibly with many iterations within it).
Another iteration around the outer scheduling loop would give rise
to a new set of sampled values.

So the bottom line is that assertions *cannot* have an infinite-
frequency clock, because we cannot have more than one timeslot at
any given moment of simulated time.

So if we are to write assertions over untimed behaviour, we must
invent a clock whose purpose is to split the simulation into
a succession of timeslots.
-- 
Jonathan Bromley, Consultant

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